The present invention relates to a method of testing an insulation property of a wafer-level chip scale package (WL-CSP), and a test element group (TEG) pattern used in the method.
In recent years, as electronic devices become smaller and more functionally sophisticated, semiconductor devices (semiconductor packages) have been required to provide multiple terminals as a consequence of miniaturization and high densification of packages thereof. In response to such request, various kinds of chip scale packages (CSPs) have been developed as miniature packages having multiple terminals.
In particular, a WL-CSP technique has gathered attention recently as a technique capable of providing an ultimate miniature package with a size similar to that of a bare chip. When the WL-CSP is produced, an insulating resin film is formed on an entire surface of a semiconductor wafer on which a plurality of integrated circuits is provided. Then, wiring patterns are formed on the insulating resin film for electrically connecting pad electrodes of the integrated circuits and external terminals such as bumps via contact holes. In the final process step, the semiconductor wafer is divided into chip-size parts.
Moreover, a semiconductor package having inductor elements within a package thereof has been introduced. Unlike conventional inductor elements that are so-called “external components” separated from a semiconductor chip, the inductor elements are formed on an insulating resin film of a WL-CSP-type semiconductor device by the use of an interconnect material relative to external terminals. The WL-CSP-type semiconductor device having the inductor elements is also expected to be an ultra-compact semiconductor package which can be applied to a frequency of hundreds of mega-hertz (MHz) to several giga-hertz (GHz) such as portable devices and wireless LAN devices.
Hereinafter, a conventional WL-CSP-type semiconductor device having an inductor element on an insulating resin film covering integrated circuits is briefly described.
On a main surface of a semiconductor chip where integrated circuits are provided, an insulating resin film is formed with a passivation film in between. In the insulating resin film, a plurality of contact holes is formed to expose pad electrodes of the integrated circuits. On the first insulating resin film, a plurality of lands having a substantially flat-circular shape is formed. Wiring patterns are formed on the insulating resin film, where each of the wiring patterns has one end connected to a corresponding contact hole and the other end connected to a corresponding land. Further, the inductor element having both terminals connected to respective pad electrodes through corresponding contact holes is formed on a region of the insulating resin film where a plurality of lands is relatively sparsely provided.
On the insulating resin film, another insulating resin is formed. The insulating resin covers the wiring patterns and the inductor element while having a plurality of openings that expose each of the lands. Over each of the openings, an external terminal is formed of a solder paste material through printing processes.    Patent Reference: Japanese Patent Publication No. 2003-347410
In the WL-CSP-type semiconductor chips, an insulation property thereof is usually tested or confirmed using a test element group (TEG) chip. FIG. 1 shows a conventional TEG chip having an insulation test pattern.
As shown in FIG. 1, two rewired lines 12 having different potentials are disposed in a comb teeth arrangement facing to each other. The rewired lines 12 having the different potentials are respectively connected to posts 18 formed over a rewiring layer 16. The rewired lines 12 are eventually connected to respective solder terminals, so that the electrical insulation property of the semiconductor chip is confirmed.
In the rewired lines 12 or the conventional insulation test pattern 12 with the comb teeth arrangement, it is difficult to accurately evaluate an insulation property of an inductor element having a rewired pattern with a spiral shape. Further, when the rewired pattern with the spiral shape is formed, as opposed to the rewired pattern with the comb teeth arrangement, it is difficult to stir an etching solution of an under bump metal (UBM) film. Consequently, it is difficult to precisely form the UBM film especially at a center region of the spiral shape, thereby degrading insulation properties. Even when the TEG chip having the insulation test pattern 12 with the comb teeth arrangement indicates good insulation quality of the chip, the chip may have an insufficient insulation in the region where the inductor element is formed.
In view of the problem described above, an object of the present invention is to provide a TEG chip capable of evaluating insulation properties with increased accuracy.
Further objects and advantages of the invention will be apparent from the following description of the invention.